Parallel Adaptive Equalizer Employing Sub-Convolution: VLSI Architecture Realized in a Field Programmable Gate Array

Abstract-This paper provides an overview of a parallel adaptive equalizer architecture and its highrate FPGA realization. The very large scale integration (VLSI) architecture for implementing a frequency domain least-mean squares (LMS) complex equalizer incorporates a simple subconvolution method, digital vector processing, specialized FFT-IFFT hardware architectures, and the discrete Fourier transform-inverse discrete Fourier transform (DFT-IDFT) overlap and save filter method. The architecture is based on recent work aimed at reducing complexity of parallel processing/filtering. A key property of the architecture is that the equalizer coefficient length may be chosen independently of the FFT-IFFT lengths and input data block lengths. The characteristics and performance of the FPGA implementation of the equalizer are presented as well as a description of the design process and computer aided development tools utilized in the process.